I don't know if this explanation will help because words. Using the photo plane as reference:
Two tools, a flat head screw driver wider than the vertical gap where the hook is, and a needle nose pliers. The screwdriver is going to be used to try to rotate the hook to the bottom left to clear the horizontal metal band, while squeezing the two bars midway to help bring the hook tip past the horizontal bar
This is true. However, the things that has me excited is that, since they are SiFive cores, they should be fully compliant with the RISC-V spec (as of the HW implementation). Other recent Linux-capable RISC-V chips, such as the T-Head C910 have been non-compliant, either due to being released before extension acceptance (Vector extension want at 1.0 before they shipped the design) or hardware design bug (floating point module does not raise underflow exceptions, causing violation of IEEE754, and non-compliance with the RISC-V spec). Issues like these have caused them to be blocked for mainline kernel support (implementing support for non-compliant chips breaks support for compliant chips or requires support of a "sub-arch").
Nonetheless, I hope this does well and helps drive improved support for newer and faster RV64 chips.
Goddamn, every day that passes I hope so much Framework get to expand their sales to more countries. I REALLY want to get one of their laptops whenever mine finally bites the dust.
The temptation is hard, but it would be totally against their philosophy, the best laptop is the one you already own, after all. Also they don't ship to Brazil yet, so no way for me to get one, unfortunately.
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