ASML sets new EUV chipmaking density record, proposes Hyper-NA tools and radical EUV speed boosts ( www.tomshardware.com )
TSMC’s debacle in the American desert ( restofworld.org )
Chip Packaging Trumps EDA: Why Synopsys Is Paying $35 Billion For Ansys ( www.nextplatform.com )
Using LLMs to Facilitate Formal Verification of RTL ( arxiv.org )
Engineers in Princeton managed to train GPT4 and extend AutoSVA to generate SVA (systemverilog assertions) from buggy RTL and functionality description. SVA is widely used to verify digital design for ASIC and FPGAs. AutoSVA2, which extends open-source AutoSVA, improves the flow to generate SVA from English description. LLM was...