Chip Design

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Intel said that its Lion cove is 10%–18% better than Redwood cove

cross-posted from: https://lemmy.world/post/16224208...

ASML sets new EUV chipmaking density record, proposes Hyper-NA tools and radical EUV speed boosts ( www.tomshardware.com )

4500 Fab Jobs Could Go Unfilled in U.S. by 2030 ( spectrum.ieee.org )

TSMC’s debacle in the American desert ( restofworld.org )

Intel Receives ASML’s First High NA EUV system ( www.youtube.com )

Meta seeks ASIC designers for ML accelerators and datacenter SoCs – Appears to be struggling to find them, even in India, as it's re-posted job ads ( www.theregister.com )

Chip Packaging Trumps EDA: Why Synopsys Is Paying $35 Billion For Ansys ( www.nextplatform.com )

Using LLMs to Facilitate Formal Verification of RTL ( arxiv.org )

Engineers in Princeton managed to train GPT4 and extend AutoSVA to generate SVA (systemverilog assertions) from buggy RTL and functionality description. SVA is widely used to verify digital design for ASIC and FPGAs. AutoSVA2, which extends open-source AutoSVA, improves the flow to generate SVA from English description. LLM was...